The progress and development of magnetoresistive random access memory (MRAM) technology has increased the viability of selecting MRAM for various embedded & standalone nonvolatile memory applications. Instead of storing data as an electric charge, MRAM stores data as magnetic moment. MRAM sensing exploits the magnetoresistive effect that occurs in magnetic tunnel junctions (MTJs). FIG. 1A is a block diagram illustrating a magnetic tunnel junction (MTJ) 10. The MTJ 10 includes a magnetic layer 101, an insulator layer 103, and a magnetic layer 102, an upper contact 104 and a lower contact 105 coupled to a substrate 100. The magnetic layers 101-102 may be constructed from a variety of transitional-metal ferromagnets and other magnetic materials, including cobalt-iron, or the like, or also from combinational layers of various synthetic antiferromagnetic (SAF) and antiferromagnetic (AFM) layers. The insulator layer 103 may also be constructed from a variety of insulating materials, such as magnesium oxide or the like. The current or voltage level applied to the MTJ 10 will control the relative magnetic orientations of the magnetic layers 101-102. In one instance, applying a particular current or voltage level will cause the magnetic orientation in the magnetic layer 101 to be anti-parallel to the magnetic orientation of the magnetic layer 102. Similarly, another current or voltage level will cause the magnetic orientations of the magnetic layers 101-102 to be the same or parallel.
When the magnetic orientations of the magnetic layers 101-102 are parallel, electrons will be more likely to tunnel through the insulator layer 103 than when the magnetic orientations are anti-parallel. This magnetoresistive effect causes the resistance of the MTJ 10 to be high when the magnetic orientations of the magnetic layers 101-102 are anti-parallel and low when the magnetic orientations are parallel. By measuring this resistance, the value of the data stored by the MTJ 10 can be determined.
In the configuration of many MTJ memories, such as the MTJ 10, one of the magnetic layers usually has a fixed magnetic orientation while the other layer is a free floating layer which is capable of having its magnetic orientation changed according to the application of the particular current or voltage.
FIG. 1B is a block diagram illustrating a programmable spin-logic device 11 based on a single MTJ element 106. A spin-logic device, such as programmable spin-logic device 11, is a configuration of one or more magnetoresistive devices into various logic elements, such as logic gates. The logic functionality is often obtained by manipulating the switching thresholds of the magnetoresistive devices and places such devices in a particular configuration. The illustrated programmable spin-logic device 11 is merely one example of such a spin-logic device that may be configured as various logic gates, such as AND, OR, NAND, NOR, and the like.
At the core of the programmable spin-logic device 11 is the MTJ element 106. The MTJ element 106 is made up of magnetic layers 107 and 108 with an insulation layer 109 placed between the two magnetic layers 107 and 108. The operation of the MTJ element 106 as a programmable element is similar to the operation described with respect to the MTJ 10 (FIG. 1A). The relative magnetic orientations of the magnetic layers 107 and 108 determine the data stored in the MTJ element 106. Writing the data to the MTJ element 106 involves application of sufficient current or voltage to switch the magnetic orientation of the free magnetic layer. In order to create a programmable logic element, three input contacts 110-112 are provided coupled to the magnetic layer 107 with an output contact 113 coupled to the magnetic layer 108.
In practice, the input contacts 110-112 are operated with positive or negative currents, ±IA, ±IB, and ±IC, of equal magnitude. The magnetic layers 107 and 108 have a magnetism, ±M1 and ±M2, respectively, where the ± reflects the magnetic orientation of either of the magnetic layers 107 and 108. The magnetic layers 107 and 108 also have different coercive fields, HC1 and HC2, respectively, where HC2 is greater than HC1. Individually, application of any of the currents IA, IB, and IC is insufficient to generate enough of a magnetic field to reverse either M1 or M2. However, when IA and IB are applied together, enough of a magnetic field is generated to reverse M1 of the magnetic layer 107, while the coercive field, HC2, is still large enough to resist reversal. When all three currents are applied together, the combined magnetic field is sufficient to reverse both M1 and M2. Therefore, by manipulating the initial set-up relationship between the magnetic layers 107 and 108, AND and OR gates may be configured using the MTJ element 106 and only the input contacts 110 and 111, and, if the third input contact 112 is used, NAND and NOR gates may be configured.
FIG. 2 is a schematic diagram illustrating the circuit equivalent of a spin torque transfer (STT) MTJ device 20. The STT MTJ device 20 may be implemented as a memory, such as a MRAM, or as some other type of spin-logic device, such as an AND gate. STT technology uses spin-aligned or polarized electrons to directly torque the physical system. Specifically, as electrons flow into a pinned thick magnetic layer, they become polarized. When these polarized electrons come near to the free layer, they will exert a torque tending to change the magnetic orientation of the nearby layer.
Because of its inherent resistance, the MTJ 200 is represented by a resistor in the schematic diagram. This resistance will cause a voltage drop, VMTJ, over the MTJ 200. The MTJ 200 is coupled on one side to a bit line 202 and on the other side to the drain contact of the transistor 201. The transistor 201 is coupled at its source contact to a source line 203 and at its gate contact to a word line 204. In order to write data to the STT MTJ device 20, a voltage, VWL, is applied to the word line 204. VWL is designed to be sufficient to turn on the transistor 201 in operational conditions.
The value written to the MTJ 200 will depend on how the STT MTJ device 20 loads the transistor 201. When there is a voltage, VBL, on the bit line 202 as the word line 204 is activated, and the source line 203 has a relative low voltage, a logical ‘1’ will be written to the MTJ 200. The current direction in the STT MTJ device 20 with this biasing arrangement produces a current flow from the bit line 202 toward the source line 203. This current direction through the MTJ 200 sets up the appropriate relative magnetic layer magnetic orientations that represent a logical ‘1’. In contrast, when a voltage, VSL, is applied to the source line 203 as the word line 204 is activated, and the bit line 202 has a relatively low voltage, the current flow in the STT MTJ device 20 is in the opposite direction (i.e., from the source line 203 toward the bit line 202). This current direction establishes the appropriate magnetic layer magnetic orientations to reflect a logical ‘0’ in the MTJ 200. Because the inherent resistance in the MTJ 200 causes a source loading effect in the write ‘0’ process, it is more difficult to write a ‘0’ in this type of configuration. Moreover, power is wasted because the voltages will be applied to the STT MTJ device 20 longer in order to trigger the state change in the MTJ 200 that produces the ‘0’.
It should be noted that the MTJ 200 may be coupled into the STT MTJ device 20 in various different ways. As illustrated in FIG. 1A, one of the magnetic layers in a MTJ, such as MTJ 200, will often have a fixed magnetic orientation, while the other magnetic layer has a free floating magnetic orientation. The current flow direction that will generally yield the highest resistance in the MTJ 200 is when the current flow travels from the fixed or reference magnetic orientation layer to the free layer. Thus, in the configuration illustrated in FIG. 2, the free floating magnetic layer side of the MTJ 200 is connected to the transistor 201, while the fixed magnetic layer side of the MTJ 200 is coupled to the bit line 202. Thus, in the write ‘0’ process when the bit line 202 is biased with a relatively low or zero voltage with respect to the source line 203, the current flows in the direction from the source line 203 to the bit line 202. The higher resistance with this direction of current flowing from the free magnetic layer to the fixed or reference magnetic layer results in a higher voltage drop, VMTJ, across the MTJ 200, which increases the source loading affect on the transistor 201, which makes it more difficult to actually write the ‘0’ to the MTJ 200. In alternative configurations, where the free magnetic layer is coupled to the bit line 202 and the reference magnetic layer is coupled to the transistor 201, the process for writing a ‘1’ would be more difficult.
FIG. 3 is a schematic diagram illustrating a magnetic memory 30. The magnetic memory 30 includes an array 300 of multiple MTJ memory units 301. The multiple MTJ memory units 301 are arranged in columns 302 within the array 300. The ellipsis 306 in the lines of the columns 302 represent the existence of multiple additional MTJ memory units 301 within the columns 302. Each of the multiple MTJ memory units 301 includes a STT MTJ structure 309 (represented as a resistor) and a transistor 310. The multiple MTJ memory units 301 are coupled to source lines 307 and bit lines 308. The multiple MTJ memory units 301 are also coupled to word lines 305 that trigger a write operation when a sufficient voltage is applied. In order to select the particular memory cell on which to write data, a series of column switches 304 are in place for each of the columns 302. A single set of source and bit line drivers 303 are used to drive each of the source lines 307 and bit lines 308 of the array 300. When a write command is received, an address is received along with it, which, when decoded, allows the magnetic memory 30 to open or close the appropriate ones of the column switches 304. The closed ones of the column switches 304 provide voltage from the source and bit line drivers 303 to the appropriate ones of the source lines 307 and the bit lines 308 corresponding to the memory cells designated by the decoded address. Thus, the voltage provided by the source and bit line drivers 303 will only be applied to the appropriate memory cell associated with the address.